The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a memory device and a method for fabricating the same.
A non-volatile memory device is a memory device that retains stored information even when not powered. Non-volatile memory devices are classified into a floating gate electrode type or a charge trap type according to a data storage scheme.
The floating gate electrode type non-volatile memory device includes a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode over a substrate. Charges are stored in or erased from the floating gate electrode so as to store data.
The charge trap type non-volatile memory device includes a tunnel insulation layer, a charge trap layer, a charge blocking layer and a gate electrode over a substrate. Charges are stored in or erased from a deep level trap site in the charge trap layer so as to store data.
Hereinafter, a structure of a conventional non-volatile memory device and problems thereof will be described in detail with reference to related figures.
FIG. 1 is a view illustrating a layout of a conventional non-volatile memory device.
Referring to FIG. 1, an active region 101 is defined by a line type device isolation layer formed in a field region 102. Over a substrate, bit lines BL are formed in a first direction A-A′, and a plurality of source select lines SSL and drain select lines DSL are formed in a second direction B-B′ intersecting the first direction A-A′. Furthermore, a plurality of word lines WL are formed between the source select lines SSL and the drain select lines DSL.
The source select line SSL represents the connection of gate electrodes of source select transistors, and a common source line CSL is formed in a junction region between the source select lines SSL. The drain select line DSL represents the connection of gate electrodes of drain select transistors, and a drain contact plug DCT is formed in a junction region between the drain select lines DSL.
FIGS. 2A to 2D illustrate cross-sectional views of a method for fabricating the conventional non-volatile memory device taken along the line A-A′ of FIG. 1.
Referring to FIG. 2A, a gate pattern of a stacked structure is formed over a substrate 200. The gate pattern includes a tunnel insulation layer 210, a floating gate electrode 220, a charge blocking layer 230 and a control gate electrode 240. The gate pattern is used as a gate line connecting gate electrodes of memory cells or as a select line SL connecting gate electrodes of select transistors.
The tunnel insulation layer 210 is provided as an energy barrier layer for the charge tunneling and, thus, is formed with an oxide layer. The floating gate electrode 220 stores data by storing or erasing charges therein or therefrom. The charge blocking layer 230 is provided to prevent charges from passing through the floating gate electrode 220 and moving upward. The charge blocking layer 230 is formed with an ONO layer constructed by sequentially stacking an oxide layer, a nitride layer and an oxide layer. For a normal transistor operation, in a select transistor, the floating gate electrode 220 and the control gate electrode 240 are connected to each other by cutting off a portion of the charge blocking layer 230. The control gate electrode 240 is formed of polysilicon.
In a subsequent process, a common source line CSL is formed in a gap region between select lines SL and extends in the second direction B-B′. Therefore, in order to secure a region where the common source line CSL is to be formed (i.e., a common source line potential region CSL′) a width W1 of the gap region between the select lines SL is greater than a width W2 of a gap region between gate lines.
However, when the pattern has a density difference, an etch rate is increased in a relatively large etch area due to a micro loading effect. Therefore, in this memory device, a width W3 of the select line SL is formed to be greater than a width of the gate line so as to prevent the micro loading effect from occurring by the density difference of the pattern. However, since the increase of the width W3 of the select line SL results in an increase of a cell area, a degree of integration of the memory device is decreased.
Referring to FIG. 2B, after forming an oxide layer for a spacer on an entire surface of a resultant structure including the gate pattern, a spacer 250 is formed on sidewalls of the gate pattern by spacer-etching the oxide layer. Since the width W2 of the gap region between the gate lines is relatively narrow, the gap region is filled with the spacer 250. Since the gap region between the select lines SL is relatively wide, a portion of the gap region is filled with the spacer 250 and a center of the gap region is exposed.
An etch stop layer 260 is formed on an entire surface of a resultant structure including the spacer 250. The etch stop layer 260 is formed with a nitride layer. The etch stop layer 260 is formed in the exposed center region between the select lines SL. That is, the etch stop layer 260 is formed on the spacer 250 that is formed on the sidewalls of the select lines SL. The etch stop layer 260 acts as an etch barrier in a subsequent process of etching an inter-insulation layer, which reduces an area of a contact hole.
Referring to FIG. 2C, an inter-insulation layer 270 is formed on an entire surface of a resultant structure including the etch stop layer 260. A line type photoresist pattern 280 is formed on the inter-insulation layer 270. The photoresist pattern 280 extends in the second direction while exposing the common source line potential region CSL′.
Referring to FIG. 2D, a contact hole is formed to expose the substrate 200 under the gap region between the select lines SL by etching the inter-insulation layer 270 using the photoresist pattern 280 as an etch barrier. During the process of etching the inter-insulation layer 270, the self-aligned etching is performed by the etch stop layer 260 formed on the sidewalls of the select lines SL so that a width W4 of the contact hole is reduced.
Subsequently, a common source line CLS 290 is formed by filling the contact hole with a conductive layer. If a width of the common source line 290 is reduced by the decrease of the width W4 of the contact hole due to the etch stop layer 260, the contact resistance of the common source line CLS is increased. According to the above processes, since it is difficult to secure a process margin of photolithography, when the photoresist pattern 280 is formed to deviate from the common source line potential region CSL′, the width of the common source line 290 is further reduced.
Although the above description is provided with reference to the floating gate electrode type non-volatile memory device, the above problems may occur in any non-volatile memory device that employs a plurality of gate lines and select lines that together construct strings.